HI-8281 Просмотр технического описания (PDF) - Holt Integrated Circuits
Номер в каталоге
Компоненты Описание
производитель
HI-8281 Datasheet PDF : 13 Pages
| |||
HI-8281
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
Figure 2 shows a block diagram of the logic section of each
receiver.
BIT TIMING
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
The ARINC 429 specification contains the following timing
specification for the received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec 10 ± 5 µsec
1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
The HI-8281 accepts signals that meet these specifications and
rejects outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word
gap, three consecutive Nulls must be found in both the upper
and lower bits of the sampling shift register. In this manner the
minimum pulse width is guaranteed.
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
Valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word program
bits or if the receiver decoder is disabled, then EOS clocks the
data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go
low. The data flag for a receiver will remain low until after both
ARINC bytes from that receiver are retrieved. This is
accomplished by activating EN with SEL, the byte selector, low
to retrieve the first byte and activating EN with SEL high to
retrieve the second byte. EN1 retrieves data from receiver 1 and
EN2 retrieves data from receiver 2.
If another ARINC word is received, and a new EOS occurs
before the two bytes are retrieved, the data is overwritten by the
new word.
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
/
LATCH
ENABLE
CONTROL
BITS 9 & 10
EOS
TO PINS
32 TO 16 DRIVER
CONTROL
BIT BD14
CLOCK
OPTION
32 BIT LATCH
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
EOS
CLOCK
CLK
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
START
SEQUENCE
CONTROL
BIT CLOCK
END
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
Share Link: 