HI-6010CM-01 Просмотр технического описания (PDF) - Holt Integrated Circuits

Номер в каталоге

Компоненты Описание

производитель

HI-6010CM-01

ARINC 429 transmitter/receiver for 8 bit bus

Holt Integrated Circuits 

HI-6010

PIN SYMBOL FUNCTION

1

VSS

2

WEF

3

CTS

4

TXC

5

HFS

6

MR

7

TXE

8

RXRDY

9

TXRDY

10

TXD0

11

TXD1

12

RXC

13

FCR

14

RXD0

15

VDD

16

RXD1

17

D0

18

D1

19

D2

20

D3

21

D4

22

D5

23

D6

24

D7

25

WE

26

CS

27

C/D

28

RE

POWER

OUTPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

OUTPUT

INPUT

POWER

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

INPUT

INPUT

INPUT

INPUT

DESCRIPTION

0.0 Volts

Error indication if high. Status register must be read to determine specific error.

Enables data transmission when low.

Source clock for data transmission. 4 times bit rate.

Hardware feature select.

Master reset, active high.

Low when transmission in progress.

High when data of received word is available.

High when data of a transmitted word may be input.

"Zeroes" data output of transmitter.

"Ones" data output of transmitter.

Source clock for data reception. 4 times bit rate.

First character received flag.

"Zeroes" data input to receiver.

5 Volts ±5%

"Ones" data input to receiver.

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

8 bit data bus input control active low.

Chip select, active low.

High for control or status register operations, low for data

8 bit data bus output control, active low.

The receiver logic is independent of the transmitter except in

the following ways:

1. Self Test

2. Parity Option

goes high for any one of three receiver errors. The status

register will show which of the three errors occurred:

Status Register Bit

Error

SR3

Received a parity error

SR4

Data Overwritten

SR5

Receiving sequence error

In self test, the transmitter outputs route to the receiver inputs

internally ignoring the external inputs. Also in self test, the

external receiver clock is replaced with the transmitter clock.

The parity option affects both the receiver and transmitter.

Either both are operational or neither.

HARDWARE CONTROL OF THE RECEIVER

PIN 2 - WEF

WEF is an error indicator. It goes high for a transmitter

"underwrite" (failure to keep up with byte loading) and pin 2

The possible Receiver sequence errors are:

1. RXD0 and RXD1 simultaneously a one.

2. Less than 32 bits before 3 nulls.

3. More than 32 bits.

There are no errors flagged for labels received that don't

match stored labels when in the label recognition mode.

Errors are cleared by MR or by reading the Status Register.

PIN 5 - HFS and the CONTROL REGISTER

This pin, along with the control register, sets up the

functioning (e.g. modes) of the chip. If HFS is low, the

HOLT INTEGRATED CIRCUITS

4-4

Share Link: