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HDMP-1012

Low Cost Gigabit Rate Transmit/Receive Chip Set

HP => Agilent Technologies 

Low Cost Gigabit Rate

Transmit/Receive Chip Set

Technical Data

HDMP-1012 Transmitter

HDMP-1014 Receiver

Features

• Transparent, Extended

Ribbon Cable Replacement

• Implemented in a Low Cost

Aluminum M-Quad 80

Package

• High-Speed Serial Rate 150-

1500 MBaud

• Standard 100K ECL

Interface

16, 17, 20, or 21 Bits Wide

• Reliable Monolithic Silicon

Bipolar Implementation

• On-chip Phase-Locked Loops

- Transmit Clock Generation

- Receive Clock Extraction

Applications

• Backplane/Bus Extender

• Video, Image Acquisition

• Point to Point Data Links

• Implement SCI-FI Standard

• Implement Serial HIPPI

Specification

Description

The HDMP-1012 transmitter and

the HDMP-1014 receiver are used

to build a high speed data link for

point to point communication.

The monolithic silicon bipolar

transmitter chip and receiver chip

are each provided in a standard

aluminum M-Quad 80 package.

From the user’s viewpoint, these

products can be thought of as

providing a “virtual ribbon cable”

interface for the transmission of

data. Parallel data loaded into the

Tx (transmitter) chip is delivered

to the Rx (receiver) chip over a

serial channel, which can be

either a coaxial copper cable or

optical link.

The chip set hides from the user

all the complexity of encoding,

multiplexing, clock extraction,

demultiplexing and decoding.

Unlike other links, the phase-

locked-loop clock extraction

circuit also transparently provides

for frame synchronization - the

user is not troubled with the

periodic insertion of frame

synchronization words. In

addition, the dc balance of the

line code is automatically

maintained by the chip set. Thus,

the user can transmit arbitrary

data without restriction. The Rx

chip also includes a state-machine

controller (SMC) that provides a

startup handshake protocol for

the duplex link configuration.

The serial data rate of the T/R link

is selectable in four ranges (see

tables on page 5), and extends

from 120 Mbits/s up to 1.25

Gbits/s. The parallel data interface

is 16 or 20 bit single-ended ECL,

pin selectable. A flag bit is

available and can be used as an

extra 17th or 21st bit under the

user’s control. The flag bit can

also be used as an even or odd

frame indicator for dual-frame

transmission. If not used, the link

performs expanded error

detection.

The serial link is synchronous,

and both frame synchronization

5962-0049E (6/94)

573

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