DS5002FP Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS5002FP Datasheet PDF : 25 Pages
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DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING
(VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6)
#
PARAMETER
40
Delay to Byte-Wide Address Valid from CE1,
CE2, or CE1N Low During Op Code Fetch
41 Pulse Width of CE1–4, PE1–4, or CE1N
42
Byte-Wide Address Hold After CE1, CE2, or
CE1N High During Op Code Fetch
43
Byte-Wide Data Setup to CE1, CE2, or CE1N
High During Op Code Fetch
SYMBOL
tCE1LPA
tCEPW
tCE1HPA
tOVCE1H
MIN
4tCLK - 35
2tCLK - 20
1tCLK + 40
MAX
30
44
Byte-Wide Data Hold After CE1, CE2, or CE1N
High During Op Code Fetch
tCE1HOV
0
45
Byte-Wide Address Hold After CE1–4, PE1–4, or
CE1N High During MOVX
tCEHDA
4tCLK - 30
46
Delay from Byte-Wide Address Valid CE1–4,
PE1–4, or CE1N Low During MOVX
tCELDA
4tCLK - 35
47
Byte-Wide Data Setup to CE1–4, PE1–4, or
CE1N High During MOVX (Read)
tDACEH
1tCLK + 40
48
Byte-Wide Data Hold After CE1–4, PE1–4, or
CE1N High During MOVX (Read)
tCEHDV
0
49
Byte-Wide Address Valid to R/W Active During
MOVX (Write)
tAVRWL
3tCLK - 35
50
Delay from R/W Low to Valid Data Out During
MOVX (Write)
tRWLDV
20
51
Valid Data Out Hold Time from CE1–4, PE1–4, or
CE1N High
tCEHDV
1tCLK - 15
52 Valid Data Out Hold Time from R/W High
53 Write Pulse Width (R/W Low Time)
tRWHDV
tRWLPW
0
6tCLK - 20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 6. Byte-Wide Bus Timing
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