DS2408 Просмотр технического описания (PDF) - Maxim Integrated

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DS2408

1-Wire 8-Channel Addressable Switch

Maxim Integrated 

DS2408

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System Requirement

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the

system and 1-Wire recovery times. The specified value here applies to systems with only one

device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an

active pullup such as that found in the DS2480B may be required.

If a 2.2kW resistor is used to pull up the data line to VPUP, 5µs after power has been applied,

the parasite capacitance does not affect normal communications.

Guaranteed by design—not production tested.

VTL, VTH are a function of the internal supply voltage.

Voltage below which, during a falling edge on I/O, a logic '0' is detected.

The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line

low.

Voltage above which, during a rising edge on I/O, a logic '1' is detected.

After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be

detected as logic '0'.

The I-V characteristic is linear for voltages less than 1V.

The earliest recognition of a negative edge is possible at tREH after VTH has been reached

before.

Highlighted numbers are NOT in compliance with the published 1-Wire standards. See

comparison table below.

Interval during the negative edge on I/O at the beginning of a presence detect pulse between

the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of

VPUP.

e represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL

to VTH.

d represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL

to the input high threshold of the bus master.

Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between

the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of

VPUP. PIO pullup resistor = 2.2kW.

Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset

(for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If

tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the

pulse will be recognized and latched.

Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.

No requirement for current balance among different pins.

STANDARD VALUES

DS2408 VALUES

PARAMETER STANDARD

OVERDRIVE

STANDARD

OVERDRIVE

NAME

SPEED

SPEED

SPEED

SPEED

MIN MAX MIN MAX MIN MAX MIN MAX

tSLOT (incl. tREC) 61µs (undef.) 7µs (undef.) 65µs 1) (undef.) 10µs (undef.)

tRSTL

480µs (undef.) 48µs 80µs 660µs 720µs 53µs 80µs

tPDH

15µs 60µs

2µs

6µs 15µs 60µs 2µs

7µs

tPDL

60µs 240µs 8µs 24µs 60µs 280µs 7µs 27µs

tW0L

60µs 120µs 6µs 16µs 60µs 120µs 8µs 13µs

tSLS, tSPD

15µs 60µs

2µs

6µs 15µs 60µs 1.8µs 8µs

1) Intentional change, longer recovery-time requirement due to modified 1-Wire front end.

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