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DM74LS161AN Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталоге
Компоненты Описание
производитель
DM74LS161AN
Fairchild
Fairchild Semiconductor Fairchild
DM74LS161AN Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
DM74LS161A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min
Max
(Note 4)
VI
Input Clamp Voltage
VOH
HIGH Level
Output Voltage
VOL
LOW Level
Output Voltage
II
Input Current @ Max
Input Voltage
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
VCC = Max
VI = 7V
Enable T
Clock
Load
1.5
2.7
3.4
0.35
0.5
0.25
0.4
0.2
0.2
0.2
Others
0.1
IIH
HIGH Level
VCC = Max
Enable T
40
Input Current
VI = 2.7V
Clock
40
Load
40
Others
20
IIL
LOW Level
VCC = Max
Enable T
0.8
Input Current
VI = 0.4V
Clock
0.8
Load
0.8
Others
0.4
IOS
Short Circuit Output Current
VCC = Max (Note 5)
20
100
ICCH
Supply Current with Outputs HIGH VCC = Max (Note 6)
18
31
ICCL
Supply Current with Outputs LOW VCC = Max (Note 7)
19
32
Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN.
Note 7: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN.
DM74LS161A Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input)
Symbol
Parameter
To (Output)
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to
Ripple Carry
Clock to
Ripple Carry
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load LOW)
Clock to Any Q
(Load LOW)
Enable T to
Ripple Carry
Enable T to
Ripple Carry
Clear to
Any Q
RL = 2 k
CL = 15 pF
CL = 50 pF
Min
Max
Min
Max
25
20
25
30
30
38
22
27
27
38
24
30
27
38
14
27
15
27
28
45
Units
V
V
V
mA
µA
mA
mA
mA
mA
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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