Logic Block Diagram (CY7C1318KV18)
CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
Burst
A0
Logic
A(19:0) 20 19
A(19:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[1:0]
Control
Logic
Write
Reg
Write
Reg
18
Read Data Reg.
36
18
18
Output
R/W
Logic
Control
C
C
Reg.
Reg. 18
Reg.
18
18
CQ
CQ
DQ[17:0]
Logic Block Diagram (CY7C1320KV18)
Burst
A0
Logic
A(18:0) 19 18
A(18:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[3:0]
Control
Logic
Write
Reg
Write
Reg
36
Read Data Reg.
72
36
36
Output
R/W
Logic
Control
C
C
Reg.
Reg. 36
Reg.
36
36
CQ
CQ
DQ[35:0]
Document Number: 001-58905 Rev. *C
Page 3 of 32
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