CY7C1316KV18 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1316KV18 Datasheet PDF : 32 Pages
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CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
Truth Table
The truth table for the CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 follow.[2, 3, 4, 5, 6, 7]
Operation
K
LD
Write cycle:
L–H
L
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L–H
L
NOP: No operation
L–H
H
Standby: Clock stopped
Stopped
X
R/W
DQ
DQ
L D(A1) at K(t + 1) D(A2) at K(t + 1)
H Q(A1) at C(t + 1) Q(A2) at C(t + 2)
X High Z
X Previous State
High Z
Previous State
Burst Address Table
(CY7C1318KV18, CY7C1320KV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1316KV18 and CY7C1318KV18 follows.[2, 8]
BWS0/ BWS1/ K
K
NWS0 NWS1
Comments
L
L L–H – During the data portion of a write sequence
CY7C1316KV18 both nibbles (D[7:0]) are written into the device.
CY7C1318KV18 both bytes (D[17:0]) are written into the device.
L
L
– L–H During the data portion of a write sequence
CY7C1316KV18 both nibbles (D[7:0]) are written into the device.
CY7C1318KV18 both bytes (D[17:0]) are written into the device.
L
H L–H – During the data portion of a write sequence
CY7C1316KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1318KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
– L–H During the data portion of a write sequence
CY7C1316KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1318KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L L–H – During the data portion of a write sequence
CY7C1316KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1318KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
– L–H During the data portion of a write sequence
CY7C1316KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1318KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H L–H – No data is written into the devices during this portion of a write operation.
H
H
– L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1318KV18 and CY7C1320KV18, ‘A1’ represents address location latched by the devices when transaction was initiated and ‘A2’ represents the addresses
sequence in the burst. On CY7C1316KV18 and CY7C1916KV18, ‘A1’ represents A + ‘0’ and ‘A2’ represents A + ‘1’.
5. ‘t’ represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the ‘t’ clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-58905 Rev. *C
Page 11 of 32
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