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CY7C1316JV18-300BZI

Cypress Semiconductor

CY7C1316JV18-300BZI Datasheet PDF : 26 Pages

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Pin Definitions (continued)

Pin Name

Pin Description

Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 22.

Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 22.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this

pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I

mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167

MHz with DDR-I timing.

TDO

Output TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

N/A