CY7C1316JV18-300BZXI Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1316JV18-300BZXI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

Logic Block Diagram (CY7C1318JV18)

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Burst

A0

Logic

A(19:0) 20 19

A(19:1)

LD

Address

Register

K

K

DOFF

CLK

Gen.

VREF

R/W

BWS[1:0]

Control

Logic

Write

Reg

Write

Reg

18

Read Data Reg.

36

18

18

Output

R/W

Logic

Control

C

C

Reg.

Reg. 18

Reg.

18

18

CQ

CQ

DQ[17:0]

Logic Block Diagram (CY7C1320JV18)

Burst

A0

Logic

A(18:0) 19 18

A(18:1)

LD

Address

Register

K

K

DOFF

CLK

Gen.

VREF

R/W

BWS[3:0]

Control

Logic

Write

Reg

Write

Reg

36

Read Data Reg.

72

36

36

Output

R/W

Logic

Control

C

C

Reg.

Reg. 36

Reg.

36

36

CQ

CQ

DQ[35:0]

Document Number: 001-15271 Rev. *B

Page 3 of 26

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