CY7C1316JV18 Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1316JV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

Logic Block Diagram (CY7C1316JV18)

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

A(19:0)

20

LD

K

K

DOFF

Address

Register

CLK

Gen.

VREF

R/W

NWS[1:0]

Control

Logic

Write

Reg

Write

Reg

8

Read Data Reg.

16

8

8

Output

R/W

Logic

Control

C

C

Reg.

Reg. 8

Reg.

8

8

CQ

CQ

DQ[7:0]

Logic Block Diagram (CY7C1916JV18)

A(19:0)

20

LD

K

K

DOFF

VREF

R/W

BWS[0]

Address

Register

CLK

Gen.

Control

Logic

Write

Reg

Write

Reg

Read Data Reg.

18

9

9

9

Output

R/W

Logic

Control

C

C

Reg.

Reg. 9

Reg.

9

9

CQ

CQ

DQ[8:0]

Document Number: 001-15271 Rev. *B

Page 2 of 26

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