CY7C1316JV18 Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1316JV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Identification Register Definitions

Instruction Field

CY7C1316JV18

Value

CY7C1916JV18

CY7C1318JV18

CY7C1320JV18

Description

Revision Number

001

001

001

001

Version number.

(31:29)

Cypress Device ID 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of

(28:12)

SRAM.

Cypress JEDEC ID

(11:1)

00000110100

00000110100

00000110100

00000110100

Allows unique

identification of

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

presence of an ID

register.

Scan Register Sizes

Instruction

Bypass

ID

Boundary Scan

Register Name

Bit Size

3

1

32

107

Instruction Codes

Instruction

EXTEST

IDCODE

Code

000

001

SAMPLE Z

010

RESERVED

011

SAMPLE/PRELOAD

100

RESERVED

101

RESERVED

110

BYPASS

111

Description

Captures the input and output ring contents.

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

Do Not Use: This instruction is reserved for future use.

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document Number: 001-15271 Rev. *B

Page 17 of 26

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