CY7C1316JV18 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1316JV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. [9]

1

TEST-LOGIC

RESET

0

0

TEST-LOGIC/

1

IDLE

SELECT

1

DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

1

1

EXIT1-DR

0

PAUSE-DR

0

1

0

EXIT2-DR

1

UPDATE-DR

1

0

1

SELECT

IR-SCAN

0

1

CAPTURE-IR

0

SHIFT-IR

0

1

1

EXIT1-IR

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

1

0

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-15271 Rev. *B

Page 14 of 26

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