CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1318BV18 Datasheet PDF : 24 Pages
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PRELIMINARY
Application Example[1]
DQ
A
SRAM#1
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
DQ
BUS
Addresses
MASTER Cycle Start#
(CPU
R/W#
or
Return CLK
ASIC) Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
SRAM#2
ZQ
DQ
CQ/CQ#
A LD# R/W# C C# K K#
R = 250ohms
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD R/W
DQ
DQ
Write Cycle:
L-H
Load address; wait one cycle; input write data on consecutive K
and K rising edges.
L L D(A1)at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Read Cycle:
L-H
Load address; wait one and a half cycle; read data on consec-
utive C and C rising edges.
L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
NOP: No Operation
L-H H X High-Z
High-Z
Standby: Clock Stopped
Stopped X X Previous State Previous State
Burst Address Table (CY7C1318BV18,
CY7C1320BV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. On CY7C1318BV18 and CY7C1320BV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1316BV18, “A1” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document Number: 38-05621 Rev. **
Page 9 of 24
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