CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C1318BV18 Datasheet PDF : 24 Pages
| |||
PRELIMINARY
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q[x:0] are automatically three-stated.
CY7C1316BV18 − DQ[7:0]
CY7C1916BV18 − DQ[8:0]
CY7C1318BV18 − DQ[17:0]
CY7C1320BV18 − DQ[35:0]
Input- Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data.
NWS0, NWS1
Input- Nibble Write Select 0, 1 − active LOW (CY7C1316BV18 only). Sampled on the rising edge of
Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1, Input- Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1916BV18 − BWS0 controls D[8:0]
CY7C1318BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1320BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input- Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316BV18 and
2M x 9 (2 arrays each of 1M x 9) for CY7C1916BV18, a single 1M x 18 array for CY7C1318BV18,
and a single array of 512K x 36 for CY7C1320BV18.
CY7C1316BV18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1916BV18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1318BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
R/W
Input- Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
Input- Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
Clock the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
Input- Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
Clock the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
K
Input- Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
Clock
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input- Negative Input Clock Input. K is used to capture synchronous data being presented to the device
Clock and to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05621 Rev. **
Page 6 of 24
Share Link: 