CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1318BV18
(Rev.:2004)

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

Logic Block Diagram (CY7C1316BV18)

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

A(19:0)

20

LD

Address

Register

K

K

DOFF

CLK

Gen.

VREF

R/W

NWS[1:0]

Control

Logic

Write

Reg

Write

Reg

Read Data Reg.

16 8

8

Output

Logic

Control

R/W

C

C

Reg.

Reg.

8

Reg.

8

8

CQ

CQ

DQ[7:0]

Logic Block Diagram (CY7C1916BV18)

A(19:0)

20

LD

Address

Register

K

K

DOFF

CLK

Gen.

VREF

R/W

BWS[0]

Control

Logic

Write

Reg

Write

Reg

Read Data Reg.

18 9

9

Output

Logic

Control

R/W

C

C

Reg.

Reg.

9

Reg.

9

9

CQ

CQ

DQ[8:0]

Document Number: 38-05621 Rev. **

Page 2 of 24

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