CY6264 Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY6264 Datasheet PDF : 9 Pages
| |||
CY6264
AC Test Loads and Waveforms
5V
OUTPUT
R1 481Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255Ω
5V
OUTPUT
R1 481Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
3.0V
10%
GND
< 5 ns
ALL INPUT PULSES
90%
90%
10%
< 5 ns
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics Over the Operating Range[3]
-55
-70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
tACE2
CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE1
OE LOW to Low Z
OE HIGH to High Z[4]
CE1 LOW to Low Z[5]
tLZCE2
tHZCE
CE2 HIGH to Low Z
CE1 HIGH to High Z[4, 6]
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
tPD
CE1 HIGH to Power-Down
WRITE CYCLE[6]
55
70
ns
55
70
ns
5
5
ns
55
70
ns
40
70
ns
25
35
ns
3
5
ns
20
30
ns
5
5
ns
3
5
ns
20
30
ns
0
0
ns
25
30
ns
tWC
Write Cycle Time
50
70
ns
tSCE1
CE1 LOW to Write End
40
60
ns
tSCE2
CE2 HIGH to Write End
30
50
ns
tAW
Address Set-Up to Write End
40
55
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
25
40
ns
tSD
Data Set-Up to Write End
25
35
ns
tHD
tHZWE
Data Hold from Write End
WE LOW to High Z[4]
0
0
ns
20
30
ns
tLZWE
WE HIGH to Low Z
5
5
ns
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 001-02367 Rev. *A
Page 3 of 9
[+] Feedback
Share Link: 