CDP1821C Просмотр технического описания (PDF) - Intersil

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производитель

CDP1821C

High-Reliability CMOS 1024-Word x 1-Bit Static RAM

Intersil 

CDP1821C/3

Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF

PARAMETER

SYMBOL

VDD

(V)

-55oC, +25oC

MIN

MAX

+125oC

MIN

MAX

Data Access Time (Note 1)

tDA

5

-

190

-

255

Read Cycle Time

tRC

5

190

-

255

-

Output Enable Time

tEN

5

65

-

90

-

Output Disable Time

tDIS

5

-

65

-

90

NOTE:

1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.

UNITS

ns

ns

ns

ns

CS

(NOTE 1)

tDOA

(NOTE 2)

A0 - A9

tRC

R/W

(NOTE 3)

DATA OUT

(NOTE 5)

(NOTE 4)

tDOH

(NOTE 5)

DATA OUT

HIGH

tAA

VALID

IMPEDANCE

NOTES:

1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.

2. Chip-Select (CS) permitted to change from low to high level or remain low.

3. Read/Write (R/W) must be at a high level during all address transitions.

4. Don’t care.

5. Data-Out (DO) is a high impedance within tDIS ns after the falling edge of R/W or the rising edge of CS.

FIGURE 1. READ CYCLE TIMING DIAGRAM

6-8

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