GS816273C Просмотр технического описания (PDF) - Giga Semiconductor
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GS816273C Datasheet PDF : 25 Pages
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Preliminary
GS816273C-250/225/200/166/150/133
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.01 12/2002
5/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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