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ADM691A

Microprocessor Supervisory Circuits

Analog Devices 

ADM691A/ADM693A/ADM800L/M

COSC

8

OSC SEL

ADM69_A

ADM800_

7

OSC IN

INPUT

POWER

R1

POWER

FAIL

INPUT

1.25V

R2

PFO

POWER

FAIL

OUTPUT

Figure 18d. Internal Oscillator (100 ms Watchdog)

WDI

WDO

t2

t3

RESET

t1

t1

t1

t1 = RESET TIME.

t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.

t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.

Figure 19. Watchdog Timing

CE Gating and RAM Write Protection

All products include memory protection circuitry which ensures

the integrity of data in memory by preventing write operations

when VCC is at an invalid level. There are two additional pins,

CEIN and CEOUT, that control the Chip Enable or Write inputs

of CMOS RAM. When VCC is present, CEOUT is a buffered rep-

lica of CEIN, with a 5 ns propagation delay. When VCC falls be-

low the reset voltage threshold, an internal gate forces CEOUT

high, independent of CEIN.

CEOUT typically drives the CE, CS, or Write input of battery

backed up CMOS RAM. This ensures the integrity of the data

in memory by preventing write operations when VCC is at an in-

valid level. Similar protection of EEPROMs can be achieved by

using the CEOUT to drive the Store or Write inputs of an

EEPROM, EAROM, or NOVRAM.

Power Fail Warning Comparator

An additional comparator is provided for early warning of fail-

ure in the microprocessor’s power supply. The Power Fail Input

(PFI) is compared to an internal +1.25 V reference. The Power

Fail Output (PFO) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider that

senses either the unregulated dc input to the system’s 5 V regu-

lator or the regulated 5 V output. The voltage divider ratio can

be chosen such that the voltage at PFI falls below 1.25 V several

milliseconds before the +5 V power supply falls below the reset

threshold. PFO is normally used to interrupt the microprocessor

so that data can be stored in RAM and the shut- down proce-

dure executed before power is lost.

Figure 20. Power Fail Comparator

Table III. Input and Output Status in Battery Backup Mode

Signal

VBATT

VOUT

VCC

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

PFI

PFO

WDI

CEOUT

CEIN

WDO

RESET

RESET

Status

Supply Current is <1 µA.

VOUT is connected to VBATT via an internal

PMOS switch.

Switchover comparator monitors VCC for

active switchover.

0 V.

Logic High. The open circuit voltage is equal

to VOUT.

Logic Low.

OSC IN is ignored.

OSC SEL is ignored.

The Power Fail Comparator remains active in

the battery-backup mode for VCC ≥ VBATT

–1.2 V. With VCC lower than this, PFO is

forced low.

The Power Fail Comparator remains active in

the battery-backup mode for VCC ≥ VBATT

–1.2 V. With VCC lower than this, PFO is

forced low.

WDI is ignored.

Logic High. The open circuit voltage is equal

to VOUT.

High Impedance.

Logic High. The open circuit voltage is equal

to VOUT.

Logic Low.

High Impedance.

REV. 0

–9–

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