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ADM693A

Microprocessor Supervisory Circuits

Analog Devices 

ADM691A/ADM693A/ADM800L/M

RAM Write Protection

The CEOUT line drives the Chip Select inputs of the CMOS

RAM. CEOUT follows CEIN as long as VCC is above the reset

threshold. If VCC falls below the reset threshold, CEOUT goes

high, independent of the logic level at CEIN. This prevents the

microprocessor from writing erroneous data into RAM during

power-up, power-down, brownouts and momentary power in-

terruptions. The LOW LINE output goes low when VCC falls

below the reset threshold.

Watchdog Timer

The microprocessor drives the WATCHDOG INPUT (WDI)

with an I/O line. When OSC IN and OSC SEL are uncon-

nected, the microprocessor must toggle the WDI pin once every

1.6 seconds to verify proper software execution. If a hardware or

software failure occurs such that WDI not toggled a 200 ms

RESET pulse will be generated after 1.6 seconds. This typi-

cally restarts the microprocessor’s power-up routine. A new

RESET pulse is issued every 1.6 seconds until WDI is again

strobed.

The WATCHDOG OUTPUT (WDO) goes low if the watch-

dog timer is not serviced within its timeout period. Once WDO

goes low it remains low until a transition occurs at WDI. The

watchdog timer feature can be disabled by leaving WDI uncon-

nected. OSC IN and OSC SEL also allow other watchdog tim-

ing options.

RESET also goes low if the Watchdog Timer is enabled and

WDI remains either high or low for longer than the watchdog

timeout period.

The RESET output has an internal 1.6 mA pullup, and can ei-

ther connect to an open collector RESET bus or directly drive a

CMOS gate without an external pullup resistor.

INPUT POWER

+5V

0.1µF

3V

BATTERY

R1

R2

NC

VCC

VBATT

BATT VOUT

ON CEOUT

ADM691A

ADM693A CEIN

ADM800L

PFI ADM800M

GND

OSC IN

OSC SEL

WDI

PFO

RESET

LOW LINE WDO

0.1µF

CMOS

RAM

ADDRESS

DECODE

RESET

A0–A15

I/O LINE

NMI µP

RESET

0.1µF

SYSTEM STATUS

INDICATORS

Figure 24. Typical Application Circuit

REV. 0

–11–

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