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ADM691A

Microprocessor Supervisory Circuits

Analog Devices 

ADM691A/ADM693A/ADM800L/M

APPLICATIONS INFORMATION

INCREASING THE DRIVE CURRENT

If the continuous output current requirements at VOUT exceeds

250 mA or if a lower VCC–VOUT voltage differential is desired, an

external PNP pass transistor may be connected in parallel with

the internal transistor. The BATT ON output can drive the

base of the external transistor via a current limiting transistor.

+5V

INPUT

POWER

0.1µF

PNP

TRANSISTOR

0.1µF

BATTERY

VCC

VBATT

BATT

ON

VOUT

Figure 21. Increasing the Drive Current

Using a Rechargeable Battery for Backup

If a capacitor or a rechargeable battery is used for backup, then

the charging resistor should be connected to VOUT since this

eliminates the discharge path that would exist during power

down if the resistor were connected to VCC.

+5V

INPUT

POWER

0.1µF

I = VOUT – VBATT

R

R

0.1µF

RECHARGEABLE

BATTERY

VCC

VOUT

VBATT ADM69_A

ADM800_

Figure 22. Rechargeable Battery

Adding Hysteresis to the Power Fail Comparator

For increased noise immunity, hysteresis may be added to the

power fail comparator. Since the comparator circuit is noninverting,

hysteresis can be added simply by connecting a resistor between

the PFO output and the PFI input as shown in Figure 23. When

PFO is low, resistor R3 sinks current from the summing junction

at the PFI pin. When PFO is high, R3 sources current into the

PFI summing junction. This results in differing trip levels for the

comparator. Resistors R1 and R2 therefore set the trip point

while R3 adds hysteresis. R3 should be larger than 10 kΩ so that

it does not cause excessive loading on the PFO output. Addi-

tional noise rejection and filtering may be achieved by adding a

capacitor from PFI to GND.

INPUT

POWER

R1

R2

5V

PFO

1.25V

PFI

TO

(PFO) µP NMI

R3

R2+R3

VH = 1.25 1+ R2 × R3 R1

VL = 1.25+R1 1.25 VCC–1.25

R2

R3

R1+R2

VMID= 1.25 R2

0V

0V

VL

VM

VIN

Figure 23. Adding Hysteresis to the Power Fail Comparator

Typical Operating Circuit

A typical operating circuit is shown in Figure 24. The circuit

features power supply monitoring, battery backup switching

and watchdog timing.

CMOS RAM is powered from VOUT . When 5 V power is

present, this is routed to VOUT. If VCC fails, then VBATT is

routed to VOUT. VOUT can supply up to 250 mA from VCC, but

if more current is required, an external PNP transistor can be

added. When VCC is higher than VBATT and the reset threshold,

BATT ON goes low, providing base drive for the external tran-

sistor. When VCC is lower than VBATT and the reset threshold,

an internal 7 Ω. MOSFET connects the backup battery to

VOUT.

Reset Output

The internal voltage detector monitors VCC and generates a

RESET output to hold the microprocessor’s RESET line low

when VCC is below the reset threshold. An internal timer holds

RESET low for 200 ms after VCC rises above the threshold.

This prevents repeated toggling of RESET even if the 5 V

power drops out and recovers with each power line cycle.

Early Power Fail Detector

The input power line is monitored via a resistive potential di-

vider connected to the Power Fail Input (PFI). When the volt-

age at PFI falls below 1.25 V, the Power Fail Output (PFO)

drives the processor’s NMI input low. If a Power Fail threshold

of 7 V is set with resistors R1 and R2, the microprocessor will

have the time when VCC drops below 7 V to save data into

RAM. Power supply capacitance will extend the time available.

This will allow more time for microprocessor housekeeping

tasks to be completed before power is lost.

–10–

REV. 0

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