74LVC132A(2006) Просмотр технического описания (PDF) - NXP Semiconductors.
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74LVC132A Datasheet PDF : 15 Pages
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NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VCC
VI
PULSE
GENERATOR
VO
DUT
RT
VEXT
RL
CL
RL
001aae331
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 8. Test data
Supply voltage
1.2 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
VCC
VCC
2.7 V
2.7 V
tr, tf
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
Load
CL
30 pF
30 pF
30 pF
50 pF
50 pF
RL
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
VEXT
tPLH, tPHL
open
open
open
open
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
GND
GND
GND
GND
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
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