3971 Просмотр технического описания (PDF) - Allegro MicroSystems

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3971

DUAL DMOS FULL-BRIDGE DRIVER

Allegro MicroSystems 

3971

DUAL DMOS

FULL-BRIDGE DRIVER

Functional Description

Charge Pump. The DMOS output stage requires a

charge pump to bring the high-side gate-source voltage

approximately 8 V above the VBB supply. Two external

components are required, a pumping capacitor connected

between CP1 and CP2 and a reservoir capacitor connected

between VBB and VCP. Ceramic 0.22 µF capacitors are

recommended.

Control Logic. Each bridge is controlled by three TTL-

compatible inputs. The inputs are resistively pulled to

ground (via 250 kΩ). A crossover-delay circuit protects

the outputs from a shoot-thru condition when going from a

forward or reverse on state to synchronous rectification/

slow decay chop (both sink drivers on). If the logic is in

the DISABLE state and changes to an on state the 415 ns

crossover delay does not occur.

Protection Circuitry. In the event of a fault due to

excessive junction temperature, or low voltage on VCP or

VDD, the outputs of the device are disabled until the fault

condition is removed.

Current Sensing. If external current-sensing circuitry

is used, the sense resistor should have an independent

ground return to the ground terminal of the device. Due to

current transients during switching, a 0.1 µF capacitor

should be connected from the sense terminal to the

batwing tab connection of the package. This capacitor

reduces voltage swings at the terminal due to the fast di/dt,

which in turn ensures that the sink driver gate-source

voltage stays within the safe operating area. Allegro

MicroSystems recommends a value of RS given by:

RS = 0.5/ITRIP max.

Thermal protection. Circuitry turns off all drivers

when the junction temperature reaches 165°C, typically.

It is intended only to protect the device from failures due

to excessive junction temperatures and should not imply

that output short circuits are permitted. Thermal shut-

down has a hysteresis of approximately 15°C.

Layout. The printed wiring board should use a heavy

ground plane. For optimum electrical and thermal perfor-

mance, the driver should be soldered directly onto the

board. If external current sensing is used, the ground side

of RS should have an individual path to the ground

terminal(s) of the device. This path should be as short as

is possible physically and should not have any other

components connected to it. The load supply terminal

should be decoupled with an electrolytic capacitor

( >47 µF is recommended) placed as close to the device as

is possible.

Parallel Operation. For high-power applications, the

two DMOS full bridges in the A3971 may be connected in

parallel as shown below. The current will be shared

equally in each full bridge due to the positive temperature

coefficient of the DMOS rDS(on).

15–50 V

1 NC

VDD 24

2

23

3

22

4

21

5

VBB1

6

20

VBB2

19

7

18

8

17

99

16

10

15

11

14

12

CHARGE PUMP

13

+5 V

15–50 V

Dwg. EP-069

www.allegromicro.com

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