24AA256-E/MFG Просмотр технического описания (PDF) - Microchip Technology

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производитель

24AA256-E/MFG

256K I2C™ CMOS Serial EEPROM

Microchip Technology 

24AA256/24LC256/24FC256

FIGURE 4-1:

(A) (B)

SCL

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(D)

(D)

(C) (A)

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

SCL

1

2

3

4

5

6

7

8

9

1

2

3

SDA

Data from transmitter

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Data from transmitter

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

© 2005 Microchip Technology Inc.

DS21203N-page 7

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