VV6300 Просмотр технического описания (PDF) - Vision
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VV6300 Datasheet PDF : 44 Pages
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VV6300 Sensor
Frame Timing
The VV6300 frame rate depends upon:
(i) the frequency of the system clock (CLKI)
(ii) the ADC conversion accuracy (8-bit or 4-bit)
(iii) the internal clock divisor selected (1, 2, 4, or 8)
(iv) the output format selected (8-wire, 4-wire, serial or UART)
User can set their own values for CLKI, the ADC conversion rate and also the clock divisor setting, subject
to achieving a frame rate up to 60 frames/sec.
The frame rate is determined in the following way:
An example is given with a clock input of 14.318MHz, 160 x120 image format, 8-bit ADC conversion rate and
a clock divisor of 2.
1. Determine clock input (CLKI) frequency - 14.318MHz
2. Pixel period = (divisor x conversion factor x output format factor) / CLKI
Clock divisor
= 1, 2, 4 or 8.
Conversion factor = 8 for 8-bit ADC accuracy
= 4 for 4-bit ADC accuracy
Output format factor = 2 for 8-wire, 4-wire, serial output modes
= 6 for UART mode
Example:
Pixel period = (2 x 8 x 2) / 14.318MHz = 2.235µs
3. Line period = (no. of visible pixels + line overhead) x pixel period
The number of visible pixels per line is 160. The interline pixel period overhead (including the 4 border pixels
that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for 60Hz mode
or 141 pixel periods for 50Hz mode.
Example:
Line period = (160 + 43) x 2.235µs = 453.705µs
4. Frame period = (no. of visible lines + frame overhead) x line period
For the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at
120. The frame overhead (which includes the 4 border lines that can be enabled to qualify extra video
information) has a constant value of 27 line periods.
Example:
Frame period
= (120 + 27) x 453.705µs = 66.694ms
Frame rate
= 1 / frame period
= 15 frames per second
cd34021-a.fm
15/01/98
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