KL5KUSB107 Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS
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KL5KUSB107 Datasheet PDF : 8 Pages
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KL5KUSB107
USB Combo - Serial & Parallel
RAM Buffer
The USB controller contains internal buffer memory. The memory is used to buffer data and USB
packets and accessed by the 16 Bit processor and the SIE. USB transactions are automatically
routed to the memory buffer. The 16-bit processor has the ability to set up pointers and block
sizes in buffer memory for USB transactions. Data is read from the interface and is processed
and packetized by the 16-bit I/O processor.
PLL Clock Generator
The PLL circuitry is provided to generate the internal 48MHz clock. This circuitry is designed to
allow use of a low cost 12 MHz external crystal which is connected to CLK and X2. If an external
12 MHz clock is available in the application, it may be used in lieu of the crystal circuit and
connected directly to the CLK input pin.
USB Interface
The USB controller meets the Universal Serial Bus (USB) specification ver 1.0/1.1. The
transceiver is capable of transmitting and receiving serial data at the USB’s full speed, 12
Mbits/sec data rate. The driver portion of the transceiver is differential, while the receive section
is comprised of a differential receiver and two single ended receivers. Internally, the transceiver
interfaces to the SIE logic. Externally, the transceiver connects to the physical layer of the USB.
Debug UART
An independent UART serial port is provided for debug and code development. The port can be
configured for a wide selection of baud rates, 7200 to 115.2K baud. The port provides transmit
and receive data support only.
Serial EEPROM Support
The USB Controller serial interface is used to provide access to external EEPROM’s. The
interface can support a variety of serial EEPROM formats.
Ver. 1.8
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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