DM9801 Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

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DM9801

1M Home Phoneline Network Physical Layer Single Chip Transceiver

Davicom Semiconductor, Inc. 

DM9801

1M Home Phoneline Network Physical Layer Single Chip Transceiver

Pin Description

Pin No. Pin Name I/O

Description

Station Interface: Receive Data, Transmit Data and Management

85

TXD0

I Transmit Data Bit 0 (MII Mode, INTFSEL = 0):

or

Transmit data input pin, bit 0, for nibble data from the MII

STXDAT

Serial Transmit Data Bit (GPSI Mode, INTFSEL = 1):

Transmit data input pin for serial data from the GPSI.

84

TXD1

I Transmit Data Bit 1 (MII Mode, INTFSEL = 0):

or

Transmit data input pin, bit 1, for nibble data from the MII

BP1

SPROM Boot Page Select 1 (GPSI Mode, INTFSEL = 1):

Most significant bit of a 2-bit encoded select. The BP1 and BP0 inputs, select

one of four, 64-byte, SPROM pages to initialize the DM9801 management

registers. Master mode must be selected using the SMODE input.

83

TXD2

I Transmit Data Bit 2 (MII Mode, INTFSEL = 0):

or

Transmit data input pin, bit 2, for nibble data from the MII

SI

Serial Data Input (GPSI Mode, INTFSEL = 1):

This is the serial data input pin to the DM9801 for the SPI bus. The SPI bus

operation is only valid if GPSI mode is selected.

82

TXD3

I Transmit Data Bit 3 (MII Mode, INTFSEL = 0):

or

Transmit data input pin, bit 3, for nibble data from the MII

SMODE

Serial Mode Select (GPSI Mode, INTFSEL = 1):

This input pin selects the SPI buses mode of operation. The SPI bus modes

of operation are:

Master Mode (SMODE = 0)

Slave Mode (SMODE = 1)

The SPI bus operation is only valid if GPSI mode is selected.

86

TX_CLK O,Z MII Transmit Clock (MII Mode, INTFSEL = 0):

or

TX_CLK is an output pin from the DM9801. Used as the transmit data

STDCLK

reference clock, to clock in nibble data from the MII when in MII interface

mode.

Serial Transmit Data Clock (GPSI Mode, INTFSEL = 1):

STDCLK is an output from the DM9801. Used as the transmit reference clock

to clock in the STXDATA when in GPSI interface mode.

81

TX_EN

I MII Transmit Enable (MII Mode, INTFSEL = 0):

or

MII Transmit enable input, used to enable the transmit function of the MII

STXEN

when in MII interface mode.

Serial Transmit Enable (GPSI Mode, INTFSEL = 1):

Used to enable the transmit function of the GPSI when in GPSI interface

mode.

66

MDC

I MII Serial Management Clock (MII Mode, INTFSEL = 0):

or

Synchronous clock to the MDIO management data input/output serial

BP0

interface which is asynchronous to transmit and receive clocks. The

maximum clock rate is 2.5MHz.

SPROM Boot Page Select 0 (GPSI Mode, INTFSEL = 1):

Least significant bit of a 2-bit encoded select. The BP1 and BP0 inputs,

select one of four, 64-byte, SPROM pages to initialize the DM9801

management registers. Master mode must be selected using the SMODE

input.

4

Preliminary

Version: DM9801-DS-P02

March 20, 2000

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