DM9801 Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

Номер в каталоге

Компоненты Описание

производитель

DM9801

1M Home Phoneline Network Physical Layer Single Chip Transceiver

Davicom Semiconductor, Inc. 

DM9801

1M Home Phoneline Network Physical Layer Single Chip Transceiver

MII Interface (continued)

RXD (receive data) is a nibble (4 bits) of data that are

sampled by the reconciliation sublayer synchronously with

respect to RX_CLK. For each RX_CLK period that

RX_DV is asserted, RXD (3:0) are transferred from the

PHY to the MAC reconciliation sublayer.

RX_CLK (receive clock) output to the MAC reconciliation

sublayer is a clock that provides the timing reference for

the transfer of the RX_DV, RXD, and RX_ER signals.

RX_DV (receive data valid) input from the PHY to indicate

the PHY is presenting recovered and decoded nibbles to

the MAC reconciliation sublayer. To interpret a receive

frame correctly by the reconciliation sublayer, RX_DV

must encompass the frame starting no later than the Start-

of-Frame delimiter and excluding any End-Stream

delimiter.

The DM9801 management functions correspond to

MII specification for IEEE 802.3u-1995 (Clause 22)

for registers 0 through 6 with vendor-specific

registers 16 through 31.

In read/write operation, the management data frame

is 64-bits long and starts with 32 contiguous logic

one bits (preamble) synchronization clock cycles on

MDC. The Start of Frame Delimiter (SFD) is

indicated by a <01> pattern followed by the

operation code (OP):<10> indicates Read operation

and <01> indicates Write operation. For read

operation, a 2-bit turnaround (TA) filing between

Register Address field and Data field is provided for

MDIO to avoid contention. Following the turnaround

time, 16-bit data is read from or written to the

management registers.

CRS (carrier sense) is asserted by the PHY when either

the transmit or receive medium is non-idle and deasserted

by the PHY when the transmit and receive medium are

idle.

MII Serial Management

The MII serial management interface consists of a

data interface, basic register set, and a serial

management interface to the register set. Through

this interface it is possible to control and configure

multiple PHY devices, get status and error

information, and determine the type and capabilities

of the attached PHY device(s).

Serial Management Interface

The serial control interface uses a simple two-wired

serial interface to obtain and control the status of

the physical layer through the MII interface. The

serial control interface consists of MDC

(Management Data Clock), and MDI/O

(Management Data Input/Output) signals.

The MDIO pin is bi-directional and may be shared

by up to 32 devices.

MII Interface Transmit and Receive Timing Diagram

TX_CLK

TX_EN

TXD

0

RX_CLK

CRS

RXD

0

RX_DV

COL

RX_CLK and TX_CLK are synchronized. All signals are inactive. The period of the two clock is 2333.3 ns.

Idle State

Figure 2

Preliminary

11

Version: DM9801-DS-P02

March 20, 2000

Share Link: