39SF512 Просмотр технического описания (PDF) - Silicon Storage Technology

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39SF512

512 Kbit (x8) Multi-Purpose Flash

Silicon Storage Technology 

512 Kbit Multi-Purpose Flash

SST39SF512

ADDRESS AMS-0

CE#

SIX-BYTE CODE FOR CHIP-ERASE

5555 2AAA

5555

5555

2AAA

5555

Data Sheet

TSCE

OE#

WE#

TWP

DQ7-0

AA

SW0

55

SW1

80

SW2

AA

SW3

55

SW4

10

SW5

1149 F17.2

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

ADDRESS A14-0

Three-byte sequence for

Software ID Entry

5555

2AAA

5555

0000

0001

CE#

OE#

WE#

TWP

DQ7-0

TWPH

AA

55

90

SW0

SW1

SW2

Device ID = B4H for SST39SF512

TIDA

TAA

BF

Device ID

FIGURE 11: SOFTWARE ID ENTRY AND READ

©2003 Silicon Storage Technology, Inc.

13

1149 F09.3

S71149-05-000

11/03

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