K9HCG08U1D Просмотр технического описания (PDF) - Samsung
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K9HCG08U1D Datasheet PDF : 74 Pages
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K9HCG08U1D K9PDG08U5D
K9LBG08U0D K9MDG08U5D
Preliminary
FLASH MEMORY
Figure 1. K9LBG08U0D Functional Block Diagram
VCC
VSS
A13 - A32
X-Buffers
Latches
& Decoders
32,768M + 1,774M Bit
NAND Flash
ARRAY
A0 - A12
Y-Buffers
Latches
& Decoders
(4,096 + 218)Byte x 1,048,576
Data Register & S/A
Y-Gating
Command
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
CLE ALE WP
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
Driver
I/0 0
I/0 7
Figure 2. K9LBG08U0D Array Organization
1,024K Pages
(=8,192 Blocks)
4K Bytes
218 Bytes
1 Block = 128 Pages
(512K + 27.25K) Bytes
1 Page = (4K + 218)Bytes
1 Block = (4K + 218)B x 128 Pages
= (512K +27.25K) Bytes
1 Device = (4K + 218)B x 128 Pages x 8,192 Blocks
= 34,512 Mbits
8 bit
Page Register
4K Bytes
I/O 0 ~ I/O 7
218 Bytes
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
I/O 0
A0
A8
A13
A21
A29
I/O 1
A1
A9
A14
A22
A30
I/O 2
A2
A10
A15
A23
A31
I/O 3
A3
A11
A16
A24
A32
I/O 4
A4
A12
A17
A25
*L
I/O 5
A5
*L
A18
A26
*L
I/O 6
A6
*L
A19
A27
*L
I/O 7
A7
*L
A20
A28
*L
Column Address
Row Address;
Page Address : A13 ~ A19
Plane Address : A20
Block Address : A21 ~ the last Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to ’Low’.
* The device ignores any additional input of address cycles than required.
* Row Address consists of Page address (A13 ~ A19) & Plane address(A20) & Block address(A21 ~ the last Address)
Samsung Confidential
10
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