R5F7131 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7131

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

Section 1 Overview

Items

On-chip ROM

On-chip RAM

Bus state controller

(BSC)

Data transfer

controller (DTC)

Interrupt controller

(INTC)

Specification

• 128 Kbytes (Only in SH7131/SH7132) or 256 Kbytes

• 8 Kbytes (Only in SH7131/SH7132) or 16 Kbytes

• Address space: A maximum 1 Mbyte for each of two areas (CS0 and

CS1) (Only in SH7132/SH7137)

• 8-bit external bus (Only in SH7132/SH7137)

• The following features settable for each area independently

⎯ Number of access wait cycles

⎯ Idle wait cycle insertion

⎯ Supports SRAM

• Outputs a chip select signal according to the target area

• Data transfer activated by an on-chip peripheral module interrupt can

be done independently of the CPU transfer.

• Transfer mode selectable for each interrupt source (transfer mode is

specified in memory)

• Multiple data transfer enabled for one activation source

• Various transfer modes

Normal mode, repeat mode, or block transfer mode can be selected.

• Data transfer size can be specified as byte, word, or longword

• The interrupt that activated the DTC can be issued to the CPU.

⎯ A CPU interrupt can be requested after one data transfer

completion.

⎯ A CPU interrupt can be requested after all specified data transfer

completion.

• Five external interrupt pins (NMI and IRQ3 to IRQ0)

• On-chip peripheral interrupts: Priority level set for each module

• Vector addresses: A vector address for each interrupt source

Rev. 3.00 Jan. 18, 2010 Page 3 of 1154

REJ09B0402-0300

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