R5F7131 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7131

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

Section 1 Overview

Table 1.1 Features of SH7131, SH7132, SH7136, and SH7137

Items

Specification

CPU

• Central processing unit with an internal 32-bit RISC (Reduced

Instruction Set Computer) architecture

• Instruction length: 16-bit fixed length for improved code efficiency

• Load-store architecture (basic operations are executed between

registers)

• Sixteen 32-bit general registers

• Five-stage pipeline

• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)

executed in two to five cycles

• C language-oriented 62 basic instructions

Note:

Some specifications on slot illegal instruction exception handling

in this LSI differ from those of the conventional SH-2. For details,

see section 5.8.4, Notes on Slot Illegal Instruction Exception

Handling.

Operating modes

• Operating modes

⎯ Single chip mode

⎯ Extended ROM enabled mode (Only in SH7132/SH7137)

⎯ Extended ROM disabled mode (Only in SH7132/SH7137)

• Operating states

⎯ Program execution state

⎯ Exception handling state

⎯ Bus release state (Only in SH7132/SH7137)

• Power-down modes

⎯ Sleep mode

⎯ Software standby mode (Only in SH7136/SH7137)

⎯ Deep software standby mode (Only in SH7136/SH7137)

⎯ Module standby mode

User break controller • Addresses, data values, type of access, and data size can all be set as

(UBC)

break conditions

• Supports a sequential break function

(SH7132 and SH7137 • Two break channels

only)

Rev. 3.00 Jan. 18, 2010 Page 2 of 1154

REJ09B0402-0300

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