PM25LV020-33SC Просмотр технического описания (PDF) - PMC-Sierra, Inc

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PM25LV020-33SC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

REGISTERS (CONTINUED)

SRWD bit: The Status Register Write Disable (SRWD)

bit is operated in conjuction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode.

When the SRWD is set to “0”, the Status Register is not

write protected. When the SRWD is set to “1” and the

WP# is pulled low (VIL), the non-volatile bits of Status

Register (SRWD, BP2, BP1, BP0) become read-only

and the WRSR instruction will be prohibited. If the SRWD

is set to “1” but WP# is pulled high (VIH), the Status

Register is still changeable by WRSR instruction.

Table 3. Status Register Format

Bit 7

SRWD

Bit 6

0

Bit 5

0

Bit 4

BP2

Bit 3

BP1

Bit 2

BP0

Bit 1

WEL

Bit 0

WIP

Table 4. Status Register Bit Definition

Bit

Bit 0

Name

WIP

Bit 1

WEL

Bit 2

BP0

Bit 3

BP1

Bit 4

BP2

Bits 5 - 6 N/A

Bit 7

SRWD

Definition

Read- Non-Volatile

/Write bit

Write In Progress Bit:

"0" indicates the device is ready

R

No

"1" indicates the write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

R/W No

Block Protection Bit: (See Table 5 and Table 6 for details)

"0" indicates the specific blocks are not write protected (default) R/W Yes

"1" indicates the specific blocks are write protected

Reserved: Always "0"s

N/A

Status Register Write Disable: (See Table 7 for details)

"0" indicates the Status Register is not write protected (default) R/W Yes

"1" indicates the Status Register is write protected

Table 5. Block Write Protect Bits for Pm25LV010/020

Status Register Bits

BP1

BP0

0

0

0

1

1

0

1

1

1 Mbit

None

Upper quarter (Block 3)

018000h - 01FFFFh

Upper half (Block 2 and 3)

010000h - 01FFFFh

All Blocks (Block 0 to 3)

000000h - 01FFFFh

2 Mbit

None

Upper quarter (Block 3)

030000h - 03FFFFh

Upper half (Block 2 and 3)

020000h - 03FFFFh

All Blocks (Block 0 to 3)

000000h - 03FFFFh

Programmable Microelectronics Corp.

8

Issue Date: July, 2005, Rev: 1.2

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