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PM25LV020-33SC Просмотр технического описания (PDF) - PMC-Sierra, Inc

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PM25LV020-33SC Datasheet PDF : 32 Pages
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PMC
Pm25LV010/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV010/020/040 devices can be serially
connected onto the SPI serial bus controlled by a SPI
Master i.e. microcontroller as shown in Figure 1. The
devices support either of the two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and the
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SPI Interface with
(0, 0) or (1, 1)
SDO
SDI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
SPI Master
(i.e. Microcontroller)
CS3 CS2 CS1
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CE#
WP# HOLD# CE# WP# HOLD# CE#
WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
Mode 0 (0, 0) SCK
Mode 3 (1, 1) SCK
SI
MSB
SO
MSB
Programmable Microelectronics Corp.
5
Issue Date: July, 2005, Rev: 1.2

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