PM25LV020-33SC Просмотр технического описания (PDF) - PMC-Sierra, Inc

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PM25LV020-33SC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

DEVICE OPERATION

The Pm25LV010/020/040 utilize an 8-bit instruction reg-

ister. Refer to Table 8 Instruction Set for the detail In-

structions and Instruction Codes. All instructions,

addresses, and data are shifted in with the most signifi-

cant bit (MSB) first on Serial Data Input (SI). The input

data on SI is latched on the rising edge of Serial Clock

(SCK) after the Chip Enable (CE#) is driven low (VIL).

Every instruction sequence starts with a one-byte in-

struction code and might be followed by address bytes,

data bytes, or address bytes and data bytes depends

on the type of instruction. The CE# must be driven high

(VIH) after the last bit of the instruction sequence has

been shifted in.

Table 8. Instruction Set

Instruction Name Instruction Format Hex Code Operation

WREN

WRDI

RDSR

WRSR

READ

FAST_READ

RDID

JEDEC ID READ

PAGE_ PROG

RDCR

WRCR

SECTOR_ER

BLOCK_ER

CHIP_ER

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 1011

1010 1011

1001 1111

0000 0010

1010 0001

1111 0001

1101 0111

1101 1000

1100 0111

06h

Write Enable

04h

Write Disable

05h

Read Status Register

01h

Write Status Register

03h

Read Data Bytes from Memory at Normal Read Mode

0Bh

Read Data Bytes from Memory at Fast Read Mode

ABh

Read Manufacturer and Product ID

9Fh

Read Manufacturer and Prduct ID by JEDEC ID Command

02h

Page Program Data Bytes Into Memory

A1h

Read Configuration Register

F1h

Write Configuration Register

D7h

Sector Erase

D8h

Block Erase

C7h

Chip Erase

HOLD OPERATION

The HOLD# is used in conjunction with the CE# to se-

lect the Pm25LV010/020/040. When the devices are

selected and a serial sequence is underway, HOLD#

can be used to pause the serial communication

with the master device without resetting the serial

sequence. To pause, the HOLD# must be brought low

while the SCK signal is low. To resume serial communi-

cation, the HOLD# is brought high while the SCK signal

is low (SCK may still toggle during HOLD). Inputs to the

Sl will be ignored while the SO is in the high impedance

state.

Programmable Microelectronics Corp.

10

Issue Date: July, 2005, Rev: 1.2

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