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SG6840

High-integrated Green Mode PWM Controller

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SG6840

Product Specification

OPERATION DESCRIPTION

Start-up Current

Typical start-up current is only 30uA This ultra low start-up

current allows users to use a high resistance, and low-

wattage, start-up resistor to supply the start-up power re-

quired by SG6840. Take a wide input-range (100VAC-

~240VAC) of AC-to-DC power adapter as an example, an 1.5

MΩ, 0.25W, start-up resistor and a 10uF/25V VDD hold-up

Operating Current

Operating current has been reduced to 3mA. The low oper-

ating current enables a better efficiency and reduces the

Green Mode Operation

The patented green-mode function provides an off-time

modulation to reduce the switching frequency in the light load

and no load conditions. The feedback voltage, which is de-

rived from the voltage feedback loop, is taken as the refer-

ence. Once the feedback voltage is lower than the threshold

voltage, switching frequency will linearly decrease until the

minimum green mode frequency around 10kHz (Ri =26kΩ).

We can find that all of the losses are in proportional to the

switching frequency, such as the switching loss of the tran-

sistor, the core loss of the transformer and inductors, and the

power loss of the snubber, etc. The off-time modulation in the

PWM controller can reduce the power consumption of the

power supply in light load and no load conditions. In normal

load and high load conditions, the PWM frequency is at its

maximum frequency around 65kHz (Ri =26kΩ) and not af-

fected by the off-time modulation.

Oscillator Operation

An external resistor Ri determines the PWM oscillation fre-

quency. A 26kΩ resistor Ri creates a 50uA constant current Ii

and generates 65kHz switching frequency.

Ii (mA) = 1.3V / Ri (kΩ);

fPWM = 1690 (kHz)

(1)

RI (kΩ)

Current sensing and PWM current limiting

SG6840 consists of two feedback loops: voltage loop and

current loop, to control the load regulation. SG6840’s cur-

rent sense input is designed for the current-mode control. A

current-to-voltage conversion is done externally through a

current-sense resistor Rs. Under normal operation, the FB

voltage VFB controls the peak voltage across the sense

resistor Rs, hence the PWM duty cycle, as follows:

Ipk = (VFB – 1.4) / 5Rs;

where

VFB is the voltage on pin FB

When the DC output voltage of secondary side decreases due

to heavy load conditions, the FB voltage VFB will increase such

that the PWM duty cycle increases to regulate the output

voltage of secondary side back to its normal voltage. The

inverting input to SG6840’s current-sense comparator is in-

ternally clamped to a variable voltage around 0.85V (note: see

Constant Output Power Limit section). The current limiting

occurs if the voltage of SENSE pin reaches this 0.85V thresh-

old value, such as Ipk (max) = 0.85V/Rs. The value of sense

resistor Rs decides the maximum power limit. Larger Rs,

whose Ipk is smaller, results in a smaller power limit

Leading Edge Blanking

Each time when the power MOSFET is switched on, a leading

spike is generated due to parasitic capacitance. To avoid

premature termination of the switching pulse, this leading

edge spike is blanked out with a time constant 270 nsec.

During this time period, the current-limit comparator is dis-

abled and cannot switch off the gate drive regardless how big

the SENSE voltage is.

Under-voltage lockout (UVLO)

The UVLO Under-Voltage Lockout (UVLO) function ensures

the supply voltage VDD for SG6840 is adequate to fully function

before enabling the output stage. The turn-on and turn-off

threshold voltages are fixed internally at 16V/10V. The hys-

teresis voltage between turn-on and turn-off prevents VDD from

being unstable during power on/off sequencing. Start-up

current is typically 30uA for efficient bootstrapping from the

rectified input for an off-line converter. During the normal

operation, VDD is developed from an auxiliary winding of the

transformer. At the moment of start-up, VDD hold-up capacitor

CIN must be charged up to 16V through the start-up resistor RIN

before enabling the output switch. With an ultra small start-up

current of 30uA, RIN can be as large as 1.5 MΩ and still be able

to charge up the hold-up capacitor CIN even when VAC =

90Vrms. Power dissipation of this large resistance RIN would

then be less than 70mW (0.07W) even under high line (VAC =

2002 System General Corporation

-7-

Ver1.0

http://www.sg.com.tw

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