RTD2120K Просмотр технического описания (PDF) - Realtek Semiconductor
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RTD2120K Datasheet PDF : 37 Pages
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Realtek
RTD2120-series
RCAP2H
CBh
TL2
CCh
TH2
CDh
1. 16-bit timer/counter with capture
The Timer 2 capture mode is the same as the 16-bit timer/counter with the addition of the capture
registers and control signals. If EXEN2 = 0, Timer2 is a 16-bit timer/counter . The C/T2 bit determines
whether the 16-bit counter counts osc cycles (divided by 4 or 12), or high-to-low transitions on the
P1.0 pin. The TR2 bit enables the counter. When the count increments from FFFFh, the TF2 flag is set.
The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-low
transition on P1.1 when EXEN2 = 1 causes the Timer 2 value to be loaded into the capture registers
(RCAP2L and RCAP2H).
2. 16-bit timer/counter with auto-reload
When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode. Control of counter input is the
same as for the other 16-bit counter modes. When the count increments from FFFFh, Timer 2 sets the
TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting
value into the RCAP2L and RCAP2H registers. When Timer 2 is in auto-reload mode, a reload can be
forced by a high-to-low transition on the P1.1 pin, if enabled by EXEN2 = 1.
3. Baud rate generator
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in
serial mode 1 or 3. In baud rate generator mode, Timer 2 functions in auto-reload mode. However,
instead of setting the TF2 flag, the counter overflow generates a shift clock for the serial port function.
As in normal auto-reload mode, the overflow also causes the preloaded start value in the RCAP2L and
RCAP2H registers to be reloaded into the TL2 and TH2 registers. When either TCLK = 1 or RCLK =
1, Timer 2 is forced into auto-reload operation, regardless of the state of the CP/RL2 bit. When
operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode, a Timer 2 interrupt
can only be generated by a high-to-low transition on the P1.1 pin setting the EXF2 bit, and only if
enabled by EXEN2 = 1.
The counter time base in baud rate generator mode is osc/2. To use an external clock source,
set C/T2 to 1 and apply the desired clock source to the P1.0 pin.
Special Function Registers(SFR)
Register Bit 7 Bit 6
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
0
0
SMOD0
TF1 TR1
GATE C/T
Bit 5
0
1
TF0
M1
Bit 4
0
1
TR0
M0
Bit 3
0
GF1
IE1
GATE
Bit 2
0
GF0
IT1
C/T
Bit 1
0
STOP
IE0
M1
Bit 0
SEL
IDLE
IT0
M0
Reset Addr
Value (Hex)
(Hex)
07 81
00 82
00 83
00 84
00 85
00 86
30 87
00 88
00 89
00 8A
confidential
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