LT3574 Просмотр технического описания (PDF) - Linear Technology

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LT3574

Isolated Flyback Converter Without an Opto-Coupler

Linear Technology 

LT3574

Applications Information

Setting the Current Limit Resistor

The maximum current limit can be set by placing a resistor

between the RILIM pin and ground. This provides some

flexibility in picking standard off-the-shelf transformers that

may be rated for less current than the LT3574’s internal

power switch current limit. If the maximum current limit

is needed, use a 10k resistor. For lower current limits, the

following equation sets the approximate current limit:

RILIM = 65 • 103(0.9A − ILIM) + 10k

The Switch Current Limit vs RILIM plot in the Typical Per-

formance Characteristics section depicts a more accurate

current limit.

Undervoltage Lockout (UVLO)

The SHDN/UVLO pin is connected to a resistive voltage

divider connected to VIN as shown in Figure 8. The voltage

threshold on the SHDN/UVLO pin for VIN rising is 1.22V.

To introduce hysteresis, the LT3574 draws 2.5µA from the

SHDN/UVLO pin when the pin is below 1.22V. The hysteresis

is therefore user-adjustable and depends on the value of

R1. The UVLO threshold for VIN rising is:

VIN(UVLO,RISING)

=

1.22V

• (R1+

R2

R2)

+

2.5µA

•

R1

The UVLO threshold for VIN falling is:

VIN(UVLO,FALLING)

=

1.22V

• (R1+

R2

R2)

To implement external run/stop control, connect a small

NMOS to the UVLO pin, as shown in Figure 8. Turning the

NMOS on grounds the UVLO pin and prevents the LT3574

from operating, and the part will draw less than a 1µA of

quiescent current.

Minimum Load Requirement

The LT3574 obtains output voltage information through

the transformer while the secondary winding is conducting

current. During this time, the output voltage (multiplied

times the turns ratio) is presented to the primary side of

the transformer. The LT3574 uses this reflected signal to

regulate the output voltage. This means that the LT3574

must turn on every so often to sample the output voltage,

which delivers a small amount of energy to the output.

This sampling places a minimum load requirement on the

output of 1% to 2% of the maximum load.

BIAS Pin Considerations

For applications with an input voltage less than 15V, the

BIAS pin is typically connected directly to the VIN pin. For

input voltages greater than 15V, it is preferred to leave the

BIAS pin separate from the VIN pin. In this condition, the

BIAS pin is regulated with an internal LDO to a voltage of

3V. By keeping the BIAS pin separate from the input voltage

at high input voltages, the physical size of the capacitors

can be minimized (the BIAS pin can then use a 6.3V or

10V rated capacitor).

SHDN/UVLO

VIN

R1

LT3574

R2

GND

RUN/STOP

CONTROL

(OPTIONAL)

3574 F08

Figure 8. Undervoltage Lockout (UVLO)

3574f

14

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