TC850IJL Просмотр технического описания (PDF) - TelCom Semiconductor Inc => Microchip

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TC850IJL

15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER

TelCom Semiconductor Inc => Microchip 

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER

1

TC850

ELECTRICAL CHARACTERISTICS (Cont.)

Symbol Parameter

Test Conditions

Min Typ Max Unit

2

tLH

Low/High Byte Access Time

CS = HIGH, CE = LOW, RD = LOW (Note 1) —

140

300 nsec

Clock Setup Time

Positive or Negative Pulse Width

100

—

— nsec

tWRE

RD Minimum Pulse Width

CS = HIGH, CE = LOW (Note 2)

450

230

— nsec

tWRD

RD Minimum Delay Time

CS = HIGH, CE = LOW (Note 2)

150

50

— nsec

tWWR

WR Minimum Pulse Width

CS = HIGH, CE = LOW, Demand Mode

75

25

— nsec

Clock Setup Time

Positive or Negative Pulse Width

100

—

— nsec

NOTES: 1. Demand mode, CONT/DEMAND = LOW. Figure 10 timing diagram. CL = 100pF.

2. Continuous mode, CONT/DEMAND = HIGH. Figure 12 timing diagram.

3. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VCC are

recommended.

3

PIN CONFIGURATIONS

CS 1

CE 2

WR 3

RD 4

CONT/DEMAND 5

OVR/POL 6

L/H 7

DB7 8

DB6 9

DB5 10

DB4 11

DB3 12

DB2 13

DB1 14

DB0 15

BUSY 16

OSC1 17

OSC2 18

TEST 19

GND 20

TC850CPL

TC850IJL

40 VDD

+

39 REF1

+

38 CREF1

–

37 CREF1

36 REF –

–

35 CREF2

34

+

CREF2

33

+

REF2

32 IN+

31 IN–

30 COMMON

29 CINTB

28 CINTA

27 CBUFA

26 CBUFB

25 BUFFER

24 INTIN

23 INTOUT

22 VSS

21 COMP

6 5 4 3 2 1 44 43 42 41 40

OVR/POL 7

L/H 8

DB7 9

DB6 10

DB5 11

39 CR–EF2

38

+

CREF2

37

+

REF2

36 IN+

35 IN–

NC 12

DB4 13

TC850CLW

TC850ILW

34 NC

33 COMMON

DB3 14

DB2 15

DB1 16

DB0 17

32 CINTB

31 CINTA

30 CBUFA

29 CBUFB

18 19 20 21 22 23 24 25 26 27 28

4

5

6

7

NC = NO INTERNAL CONNECTION

TELCOM SEMICONDUCTOR, INC.

8

3-79

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