HIP050IP Просмотр технического описания (PDF) - Intersil
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HIP050IP Datasheet PDF : 7 Pages
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HIP0050
Electrical Specifications VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pulse Width Low
t W(SCKL)
SERIAL DATA IN (SI) (Refer to Figure 1 for Waveform Detail)
-
27
175
ns
Input Setup Time
t SUI
Input Hold Time
THI
STROBE (STR)
-
1.1
75
ns
-
1.5
75
ns
Strobe Pulse Width
t W(S)
Clock to Strobe Delay
t D(CS)
SERIAL DATA OUT (SO) (Refer to Figure 1 for Waveform Detail)
-
12
150
ns
-
5
75
ns
Low Level Output Voltage
High Level Output Voltage
Propagation Delay
PROTECTION PARAMETERS
VOL
VOH
t P(CD)
Sink Current = 1.6mA
Source Current = -1.6mA
-
0.2
0.4
V
3.7
4.4
-
V
75
260
500
ns
Fault Output (FLT) Low
Over-Temp. (OT) Shutdown
OT Shutdown Hysteresis
VOL Sink Current = 1.6mA
TSD
TH
-
-
0.4
V
145
155
165
oC
5
10
20
oC
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate Zener Diode that turns on the MOSFET; holding the drain at the
output clamp voltage VOC.
2. The HIP0050 Output Drive is protected by an internal current shutdown. The ICL over-current shutdown threshold parameter specification
defines the maximum current. The minimum limit for this threshold is 300mA. The maximum current with all outputs ON may be further
limited by dissipation.
3. Package dissipation is based on thermal resistance capability in a normal operating environment. The junction to ambient thermal resis-
tance values are defined here as a PC Board mounted device with minimal copper. Due to the heat conducting capability of the DIP and
SOIC package lead frames, 35oC/W thermal resistance can be achieved with approximately 2 square inches of 1 oz. copper PC Board
area. The junction to lead thermal resistance values are based on measurements from the chip to the ground leads of the package.
SCK (CLOCK)
SI (SERIAL DATA IN)
STR (STROBE)
DRx (POWER OUTPUT DRIVER)
SO (SERIAL DATA OUT)
t W(SCK)
t W(SCK)
t SUI
t HI
t D(CS)
t P(CD)
t W(S)
t D(HL)
t D(LH)
90%
10%
tFALL, tRISE
FIGURE 1. LOGIC TIMING CONTROL WAVEFORMS
4
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