HT46R47 Просмотр технического описания (PDF) - Unspecified

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HT46R47

8-Bit OTP Battery Charger Controller

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HT46R47

status information and controls the operation

sequence.

With the exception of the TO and PD flags,

bits in the status register can be altered by

instructions like most other registers. Any

data written into the status register will not

change the TO or PD flag. In addition opera-

tions related to the status register may give

different results from those intended. The

TO flag can be affected only by system

power-up, a WDT time-out or executing the

"CLR WDT" or "HALT" instruction. The PD

flag can be affected only by executing the

"HALT" or "CLR WDT" instruction or a sys-

tem power-up.

The Z, OV, AC and C flags generally reflect the

status of the latest operations.

In addition, on entering the interrupt sequence

or executing the subroutine call, the status reg-

ister will not be pushed onto the stack automat-

ically. If the contents of the status are

important and if the subroutine can corrupt the

status register, precautions must be taken to

save it properly.

Interrupt

The device provides an external interrupt, in-

ternal timer/event counter interrupt and A/D

converter interrupts. The Interrupt Control

Register (INTC;0BH) contains the interrupt

control bits to set the enable/disable and the in-

terrupt request flags.

Once an interrupt subroutine is serviced, all

the other interrupts will be blocked (by clearing

the EMI bit). This scheme may prevent any fur-

ther interrupt nesting. Other interrupt re-

quests may happen during this interval but

only the interrupt request flag is recorded. If a

certain interrupt requires servicing within the

service routine, the EMI bit and the correspond-

ing bit of INTC may be set to allow interrupt

nesting. If the stack is full, the interrupt request

will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupts have a wake-up ca-

pability. As an interrupt is serviced, a control

transfer occurs by pushing the program counter

onto the stack, followed by a branch to a sub-

routine at specified location in the program

memory. Only the program counter is pushed

onto the stack. If the contents of the register or

status register (STATUS) are altered by the in-

terrupt service program which corrupts the de-

Labels

C

AC

Z

OV

PD

TO

¾

Bits

0

1

2

3

4

5

6, 7

Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

borrow from the high nibble into the low nibble in subtraction; otherwise AC is

cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the "CLR WDT" instruction. PD

is set by executing the "HALT" instruction.

TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in-

struction. TO is set by a WDT time-out.

Unused bit, read as "0"

Status register

Rev. 1.40

10

July 18, 2001

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