CE2766 Просмотр технического описания (PDF) - Unspecified

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производитель

CE2766

6-Channel Audio DAC, 24-bit, 192kHz

Unspecified 

CE2766

Control Register 1 (ADRS=hex01, default=hex80)

ADDR[3:0]

Hex 01

Default Value

BIT 7

AUTODET

1

BIT 6

FS384

0

CREG1[7:0]

BIT 5

CKDIV4

0

BIT 4

CKDIV2

0

BIT 3

CKdet

0

BIT 2

MUTE56

0

BIT 1

MUTE34

0

BIT 0

MUTE12

0

AUTODET Automatically detects the serial audio input data sampling rate clock frequency.

0: - do not use auto-detect

1: - automatically detects the serial audio input data sampling rate and clock frequency.

FS384: 384 fs or 256 fs control for the PLL clock output. This bit is recognized only when “AUTODET” bit is set to ‘0’

otherwise the input format is automatically detected.

0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock

1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock

CKDIV4: Clock divider enable control.This bit is recognized only when “AUTODET” bit is set to ‘0’ otherwise the input

format is automatically detected.

0: do not enable input clock divided by 4

1: enable input clock divided by 4

CKDIV2: Clock divider enable control . This bit is recognized only when “AUTODET” bit is set to ‘0’ otherwise the

input format is automatically detected.

0: do not enable input clock divided by 2

1: enable input clock divided by 2

CKdet: turn off clock detection.

0: enable clock detection. The chip will be in reset mode when there are no clock.

1: disable clock detection.

MUTE56: Mute control for channels 5 and 6

0: do not mute channels 5 and 6

1: simultaneously mute channels 5 and 6

MUTE34: Mute control for channels 3 and 4

0: do not mute channels 3 and 4

1: simultaneously mute channels 3 and 4

MUTE12: Mute control for channels 1 and 2

0: do not mute channels 1 and 2

1: simultaneously mute channels1 and2

11-19

June 25, 2005

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