AD6657BBCZRL(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD6657BBCZRL Datasheet PDF : 32 Pages
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AD6657
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 5.
Parameter
Description
Min
Typ
Max Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK setup time
0.24
ns
tHSYNC
SYNC to rising edge of CLK hold time
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK 2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to 10
ns
an output relative to the SCLK falling edge
tDIS_SDIO
Time required for the SDIO pin to switch from an output to 10
ns
an input relative to the SCLK rising edge
Timing Diagrams
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
CLK–
DCO+
DCO–
D10+AB (MSB)
D10–AB (MSB)
tCH
tCL
1/fS
tDCO
D10A
D10B
D10A
tSKEW
tPD
D10B D10A D10B
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D0+AB (LSB)
D0–AB (LSB)
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)
CLK+
SYNC
tSSYNC
tHSYNC
Figure 3. SYNC Input Timing Requirements
Rev. 0 | Page 8 of 32
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