RTL8196E Просмотр технического описания (PDF) - Realtek Semiconductor

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RTL8196E

5-PORT 10/100M ETHERNET ROUTER NETWORK PROCESSOR

Realtek Semiconductor 

RTL8196E

Datasheet

List of Tables

TABLE 1. PIN DESCRIPTIONS .......................................................................................................................................................6

TABLE 2. CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................10

TABLE 3. SHARED I/O PIN MAPPING .........................................................................................................................................11

TABLE 4. MEMORY CONTROL REGISTER (MCR) (0XB800_1000) ............................................................................................14

TABLE 5. DRAM CONFIGURATION REGISTER (DCR) (0XB800_1004).....................................................................................15

TABLE 6. DRAM TIMING REGISTER (DTR) (0XB800_1008)....................................................................................................16

TABLE 7. DDR DRAM CALIBRATION REGISTER (DDCR) (0XB800_1050) .............................................................................17

TABLE 8. SPI FLASH CONFIGURATION REGISTER (SFCR) (0XB800_1200) ..............................................................................18

TABLE 9. SPI FLASH CONFIGURATION REGISTER 2 (SPCR2) (0XB800_1204) .........................................................................18

TABLE 10. SPI FLASH CONTROL & STATUS REGISTER (SFCSR) (0XB800_1208) .....................................................................19

TABLE 11. SPI FLASH DATA REGISTER (SFDR) (0XB800_120C) ..............................................................................................20

TABLE 12. SPI FLASH DATA REGISTER 2 (SFDR2) (0XB800_1210) ..........................................................................................20

TABLE 13. INTERRUPT CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_3000) ...........................................................21

TABLE 14. GLOBAL INTERRUPT MASK REGISTER (GIMR) (0X B800_3000) ..............................................................................21

TABLE 15. GLOBAL INTERRUPT STATUS REGISTER (GISR) (0X B800_3004).............................................................................22

TABLE 16. INTERRUPT ROUTING REGISTER 1 (IRR1) (0XB800_300C) ......................................................................................22

TABLE 17. INTERRUPT ROUTING REGISTER 2 (IRR2) (0XB800_3010) .......................................................................................23

TABLE 18. INTERRUPT ROUTING REGISTER 3 (IRR3) (0XB800_3014) .......................................................................................23

TABLE 19. TIMER CONTROL ADDRESS MAPPING (BASE: 0XB800_3100) ...................................................................................24

TABLE 20. TIMER/COUNTER 0 DATA REGISTER (0XB800_3100) ...............................................................................................24

TABLE 21. TIMER/COUNTER 1 DATA REGISTER (0XB800_3104) ...............................................................................................24

TABLE 22. TIMER/COUNTER 0 COUNTER REGISTER (0XB800_3108) .........................................................................................25

TABLE 23. TIMER/COUNTER 1 COUNTER REGISTER (0XB800_310C).........................................................................................25

TABLE 24. TIMER/COUNTER CONTROL REGISTER (0XB800_3110) ............................................................................................25

TABLE 25. TIMER/COUNTER INTERRUPT REGISTER (0XB800_3114)..........................................................................................25

TABLE 26. CLOCK DIVISION BASE REGISTER (0XB800_3118) ...................................................................................................26

TABLE 27. WATCHDOG TIMER CONTROL REGISTER (0XB800_311C)........................................................................................26

TABLE 28. GPIO REGISTER SET (0XB800_3500) .......................................................................................................................27

TABLE 29. GPIO PORT A, B, C, D CONTROL REGISTER (PABCD_CNR) (0XB800_3500) ........................................................28

TABLE 30. GPIO PORT A, B, C, D DIRECTION REGISTER (PABCD_DIR) (0XB800_3508)........................................................28

TABLE 31. PORT A, B, C, D DATA REGISTER (PABCD_DAT) (0XB800_350C)........................................................................28

TABLE 32. PORT A, B, C, D INTERRUPT STATUS REGISTER (PABCD_ISR) (0XB800_3510) .....................................................29

TABLE 33. PORT A, B INTERRUPT MASK REGISTER (PAB_IMR) (0XB800_3514).....................................................................29

TABLE 34. PORT C, D INTERRUPT MASK REGISTER (PCD_IMR) (0XB800_3518).....................................................................30

TABLE 35. SHARED PIN REGISTER (PIN_MUX_SEL) (0XB800_0040)......................................................................................31

TABLE 36. SHARED PIN REGISTER (PIN_MUX_SEL_2) (0XB800_0044)..................................................................................32

TABLE 37. UART CONTROL INTERFACE PINS ............................................................................................................................33

TABLE 38. UART CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_2000) ..................................................................33

TABLE 39. UART RECEIVER BUFFER REGISTER (DLAB=0) (0XB800_2100, 0XB800_2000) ...................................................34

TABLE 40. UART TRANSMITTER HOLDING REGISTER (DLAB=0) (0XB800_2100, 0XB800_2000) ..........................................34

TABLE 41. UART DIVISOR LATCH LSB (DLAB=1) (0XB800_2100, 0XB800_2000)................................................................34

TABLE 42. UART DIVISOR LATCH MSB (DLAB=1) (0XB800_2104, 0XB800_2004)...............................................................34

TABLE 43. UART INTERRUPT ENABLE REGISTER (DLAB=0) (0XB800_2104, 0XB800_2004) .................................................35

TABLE 44. UART INTERRUPT IDENTIFICATION REGISTER (0XB800_2108, 0XB800_2008) .......................................................35

TABLE 45. UART FIFO CONTROL REGISTER (0XB800_2108, 0XB800_2008) ..........................................................................35

TABLE 46. UART LINE CONTROL REGISTER (0XB800_210C, 0XB800_200C)..........................................................................36

TABLE 47. UART MODEM CONTROL REGISTER (0XB800_2110, 0XB800_2010) ......................................................................36

TABLE 48. UART LINE STATUS REGISTER (0XB800_2114, 0XB800_2014) ..............................................................................36

TABLE 49. UART MODEM STATUS REGISTER (0XB800_2110, 0XB800_2018) .........................................................................37

TABLE 50. DIVISOR LATCH VALUE EXAMPLES...........................................................................................................................37

TABLE 51. PCIE PORT 0 HOST MODE EXTENDED REGISTER ADDRESS MAPPING (BASE: 0XB8B0_1000)..................................39

TABLE 52. PCIE MDIO REGISTER (0XB8B0_1000) ...................................................................................................................39

5-Port 10/100M Ethernet Router Network Processor

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Track ID: JATR-3375-16 Rev. 1.0

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