RTL8196E Просмотр технического описания (PDF) - Realtek Semiconductor
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RTL8196E Datasheet PDF : 79 Pages
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RTL8196E
Datasheet
8.3. GPIO CONTROL .........................................................................................................................................................27
8.3.1. GPIO Register Set (0xB800_3500).......................................................................................................................27
8.3.2. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)............................................................28
8.3.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800_3508)..........................................................28
8.3.4. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C) ..........................................................................28
8.3.5. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510) ...........................................................29
8.3.6. Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514) ..........................................................................29
8.3.7. Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518).........................................................................30
8.4. GPIO SHARED PIN CONFIGURED MAPPING LIST........................................................................................................31
8.4.1. Shared Pin Register (PIN_MUX_SEL) (0xB800_0040) .......................................................................................31
8.4.2. Shared Pin Register (PIN_MUX_SEL_2) (0xB800_0044) ...................................................................................32
9. UART.................................................................................................................................................................................33
9.1. FEATURES ..................................................................................................................................................................33
9.2. INTERFACE PINS.........................................................................................................................................................33
9.3. UART CONTROL REGISTER .......................................................................................................................................33
9.3.1. UART Control Register Address Mapping (Base: 0xB800_2000)........................................................................33
9.3.2. UART Receiver Buffer Register (DLAB=0) (0xB800_2100, 0xB800_2000) ........................................................34
9.3.3. UART Transmitter Holding Register (DLAB=0) (0xB800_2100, 0xB800_2000) ................................................34
9.3.4. UART Divisor Latch LSB (DLAB=1) (0xB800_2100, 0xB800_2000) .................................................................34
9.3.5. UART Divisor Latch MSB (DLAB=1) (0xB800_2104, 0xB800_2004) ................................................................34
9.3.6. UART Interrupt Enable Register (DLAB=0) (0xB800_2104, 0xB800_2004) ......................................................35
9.3.7. UART Interrupt Identification Register (0xB800_2108, 0xB800_2008) ..............................................................35
9.3.8. UART FIFO Control Register (0xB800_2108, 0xB800_2008).............................................................................35
9.3.9. UART Line Control Register (0xB800_210C, 0xB800_200C) .............................................................................36
9.3.10. UART Modem Control Register (0xB800_2110, 0xB800_2010) .....................................................................36
9.3.11. UART Line Status Register (0xB800_2114, 0xB800_2014) ............................................................................36
9.3.12. UART Modem Status Register (0xB800_2110, 0xB800_2018)........................................................................37
9.4. BAUD RATE ...............................................................................................................................................................37
10. PCI EXPRESS BUS INTERFACE.............................................................................................................................38
10.1. PCI EXPRESS TRANSMITTER ......................................................................................................................................38
10.2. PCI EXPRESS RECEIVER.............................................................................................................................................38
10.3. PCI EXPRESS HOST MODE .........................................................................................................................................39
10.3.1. PCIe Port 0 Host Mode Extended Register Address Mapping (Base: 0xB8B0_1000) ....................................39
10.3.2. PCIe MDIO Register (0xB8B0_1000) .............................................................................................................39
10.3.3. PCIe Interrupt Status Register (0xB8B0_1004)...............................................................................................39
10.3.4. PCIe Power Control Register (0xB8B0_1008)................................................................................................40
10.3.5. PCIe IP Configuration Register (0xB8B0_100C)............................................................................................40
10.3.6. PCIe SRAM BIST Check Register (0xB8B0_1010)..........................................................................................40
11. SWITCH CORE CONTROL......................................................................................................................................41
11.1. GLOBAL PORT CONTROL REGISTER ...........................................................................................................................41
11.1.1. Global Port Control Register Address Mapping (Base: 0xBB80_4000) .........................................................41
11.1.2. Global MDC/MDIO Command Register (0xBB80_4004) ...............................................................................41
11.1.3. Global MDC/MDIO Status Register (0xBB80_4008)......................................................................................42
11.1.4. Global Frame Filtering Control Register Address Mapping (Base: 0xBB80_4000).......................................42
11.1.5. Global Broadcast Storm Control Register (0xBB80_4044).............................................................................42
11.2. PER-PORT CONFIGURATION REGISTER.......................................................................................................................43
11.2.1. Port Interface Type Control Register (0xBB80_4100) ....................................................................................43
11.2.2. Port Configuration Register of Port N (N=0~4) .............................................................................................44
11.2.3. Port Status Register of Port N (N=0~4) ..........................................................................................................47
12. GREEN ETHERNET ..................................................................................................................................................48
12.1. CABLE LENGTH POWER SAVING ................................................................................................................................48
5-Port 10/100M Ethernet Router Network Processor
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Track ID: JATR-3375-16 Rev. 1.0
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