RTL8196E Просмотр технического описания (PDF) - Realtek Semiconductor
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RTL8196E Datasheet PDF : 79 Pages
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RTL8196E
Datasheet
Pin Name
WE#
LDQM
UDQM
MCLK
MCLK#
MCLKE
MCS0#
BS[2:0]
RAS#
CAS#
WE#
LDQM
UDQM
DDR_LDQS
DDR_UDQS
VREF
DDR_ODT
SF_CS0#
SF_SDIO[1:0]
SF_SCK
U0_TX
U0_RX
U1_TX
U1_RX
U1_RTS#
U1_CTS#
JTAG_TCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
Pin No.
82
54
69
65
66
85
83
84, 35, 36
80
81
82
54
69
63
70
34
86
123
122, 121
120
125
126
1
127
128
2
127
2
1
128
Type Description
O Write Enable for SDR DRAM.
O Lower Data Mask Output to SDR DRAM.
Corresponds to D[7:0]
O Upper Data Mask Output to SDR DRAM.
Corresponds to D[15:8]
DDR DRAM Control
O DDR DRAM Differential Clock.
O DDR DRAM Differential Clock.
O DDR DRAM Clock Enable.
O DDR DRAM Chip Select 0.
O DDR DRAM Chip Bank Select [2:0].
O Raw Address Strobe (RAS#) for DDR DRAM.
O Column Address Strobe for DDR DRAM.
O Write Enable for DDR DRAM.
O Lower Data Mask Output to DDR DRAM.
Corresponds to D[7:0]
O Upper Data mask output to DDR DRAM.
Corresponds to D[15:8]
O Lower Data Strobe to DDR DRAM.
Corresponds to D[7:0]
O Upper Data strobe to DDR DRAM.
Corresponds to D[15:8]
AI Voltage Reference 1.25V for DDR1.
Voltage Reference 0.9V for DDR2.
O DDR2 On-Die Termination.
ODT (registered HIGH) enables termination resistance
internal to the DDR2 DRAM.
Serial SPI Flash Control
O SPI Serial Flash Chip Select 0.
I/O SPI Serial Flash Serial Data Input/Output.
O SPI Serial Flash Serial Clock Output.
SF_SDI will be driven on the falling edge.
SF_SDO will be latched on the rising edge.
UART
O Data Transmit Serial Output of UART0.
IPU Data Receive Serial Input of UART0.
O Data Transmit Serial Output of UART1.
IPU Data Receive Serial Input of UART1.
O Request to Send of UART1.
I Clear to Send of UART1.
JTAG
IPU JTAG Test Clock.
IPU JTAG Test Mode Select.
O JTAG Test Data Output.
IPU JTAG Test Data In.
5-Port 10/100M Ethernet Router Network Processor
7
Track ID: JATR-3375-16 Rev. 1.0
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