MB15F76UV Просмотр технического описания (PDF) - Unspecified

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MB15F76UV

ASSP Dual Serial Input PLL Frequency Synthesizer(Small Package)

Unspecified 

MB15F76UV

Aug. 2003

Edition 0.2

Table.4 Binary 13-bit Programmable Counter Data Setting

Divide

ratio

(N)

NNNNNNNNN

13 12 11 10 9 8 7 6 5

3

000000000

4

000000000

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

8191

111111111

Note: • Divide ratio less than 3 is prohibited.

Table.5 Binary 5-bit Swallow Counter Data Setting

Divide

ratio

(N)

AAAAA

54321

0

00000

1

00001

⋅

⋅

⋅

⋅

⋅

⋅

31

11111

Note: • Divide ratio (A) range = 0 to 31

Table. 6 Prescaler Data Setting

SW = ”1”

Prescaler

divide ratio

IF-PLL

RF-PLL

4/5

16/17

SW = ”0”

8/9

32/33

Table. 7 Phase Comparator Phase Switching Data Setting

FCIF,RF = 1

FCIF,RF = 0

DoIF,RF

fr > fp

H

L

fr = fp

Z

Z

fr < fp

L

H

VCO Output

Frequency

VCO polarity

1

2

Note: • Z = High–impedance

• Depending upon the VCO and LPF polarity,

FC bit should be set.

NNNN

4321

0011

0100

⋅

⋅

⋅

⋅

1111

1

2

VCO Input Voltage

10

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