WS57C45 Просмотр технического описания (PDF) - STMicroelectronics
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WS57C45 Datasheet PDF : 9 Pages
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WS57C45
Synchronous Enable Programming
The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in
the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by
programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a
super voltage. Referring to the Mode Selection table, VPP is applied to A1 followed by VIH applied to A2. This
procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is
programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to
how synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable Verification
The WS57C45’s synchronous enable function is verified operationally. Apply power for read operation with OE/OES
and INIT/VPP at VIH and take the clock (CP/PGM) from VIL to VIH. The output data bus should be in a high
impedance state. Next take OE/OES to VIL. The outputs will remain in the high impedance state. Take the clock
(CP/PGM) from VIL to VIH and the outputs will now contain the data that is present. Take OE/OES to VIH. The output
should remain driven. Clocking CP/PGM once more from VIL to VIH should place the outputs again in a high
impedance state.
Blank Check
Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all
2048 bytes in the ‘0’ state. “1’s” are loaded into the WS57C45 through the procedure of programming.
MODE
READ OR OUTPUT DISABLE
PIN FUNCTION
A2 CP/PGM (OE/OES)/VFY INIT/VPP
Read (Note 6)
Output Disable
Program (Notes 5 & 7)
Program Verify (Notes 5 & 7)
Program Inhibit (Notes 5 & 7)
Intelligent Program (Notes 5 & 7)
Program Synch Enable (Note 7)
Program Initial Byte (Note 7)
Initial Byte Read
X
X
VI L
X
X
VI H
X
VI L
VI H
X
VI H
VI L
X
VI H
VI H
X
VI L
VI H
VI H
VI L
VI H
VI L
VI L
VI H
X
X
VI L
VI H
VI H
VPP
VPP
VPP
VPP
VPP
VPP
VI L
NOTES: 5. X = Don’t Care but not to exceed VPP.
6. During read operation, the output latches are loaded on a “0” to “1” transition of CP.
7. During programming and verification, all unspecified pins to be at VIL.
OUTPUTS
A1
X Data Out
X
High Z
X
Data In
X Data Out
X
High Z
X
Data In
VPP High Z
VPP Data In
X Data Out
2-26
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