STLC3055Q Просмотр технического описания (PDF) - STMicroelectronics

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STLC3055Q

WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT

STMicroelectronics 

STLC3055

PIN DESCRIPTION (continued)

N.

Name

Function

4

PD

Power Down input. Normally connected to CVCC (or to logic level high). Can be used to set

TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0.

26

CVCC Internal positive voltage supply filter.

35

VBAT Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted

to VBAT1.

23

GATE Driver for external Power MOS transistor.

21

VF

Feedback input for DC/DC converter controller.

22

CLK

Power Switch Controller Clock (typ. 125KHz). From version marked STLC3055 A5, this pin

can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an

internal auto-oscillation is internally generated and it is used instead of the external clock.

When the CLK pin is connected to AGND, the GATE output is disabled.

24 RSENSE Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS

pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.

1

D0

Control Interface: input bit 0.

2

D1

Control Interface: input bit 1.

3

D2

Control interface: input bit 2.

8

DET

Logic interface output of the supervision detector (active low).

33

CSVR Battery supply filter capacitor.

12

RTTX Metering pulse cancellation buffer output. TTX filter network should be connected to this point.

If not used should be left open.

13

FTTX Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.

10

CTTX1 Metering burst shaping external capacitor.

11

CTTX2 Metering burst shaping external capacitor.

9

CKTTX Metering pulse clock input (12 KHz or 16KHz square wave).

44

VBAT1 Frame connection. Must be shorted to VBAT.

5

RES

Reserved, must be connected to AGND.

6, 7,36,

NC

38,39,

40,42

Not connected.

FUNCTIONAL DESCRIPTION

The STLC3055 is a device specifically developed

for WLL and ISDN-TA applications.

It is based on a SLIC core, on purpose optimised

for these applications, with the addition of a

DC/DC converter controller to fulfil the WLL and

ISDN-TA design requirements.

The SLIC performs the standard feeding, signal-

ling and transmission functions.

It can be set in three different operating modes

via the D0, D1, D2 pins of the control logic inter-

face (0 to 3.3V logic levels). The loop status is

carried out on the DET pin (active low).

High Impedance Feeding (HI-Z)

Active

Ringing

Table 1 shows how to set the different SLIC oper-

ating modes.

Table 1. SLIC operating modes.

PD D0 D1 D2

Operating Mode

0 0 0 X Power Down

1 0 0 X H.I. Feeding (HI-Z)

1 0 1 0 Active Normal Polarity

The DET pin is an open drain output to allow easy

interfacing with both 3.3V and 5V logic levels.

The four possible SLIC’s operating modes are:

1 0 1 1 Active Reverse Polarity

1 1 1 0 Active TTX injection (N.P.)

1 1 1 1 Active TTX injection (R.P.)

Power Down

1 1 0 0/1 Ring (D2 bit toggles @ fring)

4/22

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